An integrated circuit (IC) has a large number of electronic components, such as transistors, logic gates, diodes, and wires, that are fabricated by forming layers of different materials and of different geometric shapes on various regions of a silicon wafer.
Many phases of physical design may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. To design an integrated circuit, a designer first creates high level behavior descriptions of the IC device using a high-level hardware design language. An EDA system typically receives the high level behavior descriptions of the IC device and translates this high-level design language into netlists of various levels of abstraction using a computer synthesis process. A netlist describes interconnections of nodes and components on the chip and includes information of circuit primitives such as transistors and diodes, their sizes and interconnections, for example.
An integrated circuit designer may use a set of layout EDA application programs to create a physical design of the IC from the logical design. The layout EDA application uses geometric shapes of different materials to create the various electrical components on an integrated circuit and to represent electronic and circuit IC components as geometric objects with varying shapes and sizes. The geometric information about the placement of the nodes and components onto the chip may be determined by a placement process and a routing process. The placement process is a process for placing electronic components or circuit blocks on the chip and the routing process is the process for creating interconnections between the blocks and components according to the specified netlist.
After an integrated circuit designer has created an initial integrated circuit layout, the designer then verifies and optimizes the integrated circuit layout using a set of EDA testing and analysis tools. Verification may include, for example, design rule checking to verify compliance with rules established for various IC parameters.
With modem EDA design tools, both the initial process of generating a layout and the later process of correcting problems within a layout are usually performed with automated approaches. The automated approaches will result in the placement of geometric features within the layout without requiring manual intervention by a user regarding selection of the specific combination of patterns that is to be used on the layout.
The problem with these automated approaches is that there may be many different combinations of legal placement options for the layout, and the particular placement option selected by the system may not be the exact option that the user would have selected if given the choice. In fact, the user may not have even been informed that there are alternate options that could have been legally used by the system.